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1 for more information www.linear.com/LTC3305 typical application features description lead-acid battery balancer the lt c ? 3305 balances up to 4 lead-acid batteries connected in series. it is intended to be used in conjunction with a separate pre-existing battery charger as part of a high performance battery system. all voltage monitoring, gate drive, and fault detection circuitry is integrated. the LTC3305 employs an auxiliary battery or an alternative storage cell to transfer charge to or from each individual battery in the stack. a mode pin provides two operating modes, timer mode and continuous mode. in timer mode, once the balancing operation is completed, the LTC3305 goes into a low power state for a programmed time and then periodically rebalances the batteries. in continuous mode, the balancing operation continues even after the batteries are balanced to their programmed termination voltage. the LTC3305 is available in a thermally enhanced 38-lead tssop package. 4- battery balancer with programmed high and low battery voltage faults battery voltages converge over time applications n single ic balances up to four 12v lead-acid batteries in series n all nfet design n stackable to balance larger series battery packs n standalone balancing operation: requires no external p or additional control circuitry n balancing current limited by external ptc thermistor n continuous mode and timer mode n programmable uv and ov fault thresholds n programmable termination time and termination voltage n thermally enhanced 38-lead tssop package n telecom backup systems n home battery powered backup systems n industrial electric vehicles n energy storage systems (ess) n medical equipment l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. battery 4 battery 3 battery 2 battery 1 time 3305 ta01a 16 14 12 10 8 6 4 2 0 battery voltage (v) v reg en1 en2 mode term1 term2 done batx baty cton ctoff ctbat v l v h gnd LTC3305 auxn auxp v1 v2 v3 v4 cm cp boost ngate1-9 i set uvflt ovflt bal ptcflt 10f 25v 10f 25v 10f 25v 10nf 100nf 10nf 27.4k 6.04k 1.33k 100k each 249 6.04k 3.01k 6.04k 6.04k 42.2k 12.1k 10f 25v 10f 25v 9 6.04k 6.04k 6.04k 6.04k 1f 6v 10f 25v ngate5 ngate6 ngate7 ngate8 ngate9 3305 ta01 ptc aux 10f 25v ngate4 ngate3 ngate2 ngate1 bat4 bat3 bat2 bat1 + + + + + i charge battery stack charger charger supply lt c3305 3305fb
2 for more information www.linear.com/LTC3305 pin configuration absolute maximum ratings stack voltage, v4 to gnd ......................................... 68v battery voltages, v4 to v3 , v3 to v2 , v2 to v1 , v1 to gnd .................................................. C 0.3v to 20v auxiliary cell voltage, auxp to auxn ........ C 0.3v to 20v v reg voltage ................................................ C 0.3v to 6v v h , v l voltage ..... C 0.3v to lesser of 6v or (v reg + 0.3v ) uv flt , ov flt , ptc flt , bal , done , batx, baty voltage ............................................... C 0.3v to 6v e n1 , e n2 , mode, ter m1 , ter m2 voltage ................ C 0.3v to lesser of 6v or (v reg + 0.3v ) ngat e1 , ngat e2 , ngat e3 , ngat e4 , ngat e8 , ngat e9 voltage .............. C 0.3v to lesser of 68v or ( v4 + 0.3v ) ngat e5 , ngat e6 , ngat e7 voltage .............. (greater of C 0.3v or boost C 68v ) to (boost+ 0.3v )* uv flt , ov flt , ptc flt , bal , done , batx, baty current ......................................................... 10ma i set current .............................................................. 1ma cp, cm current ....................................................... 50ma operating junction temperature range (notes 2, 3) ............................................ C 40 c to 125 c storage temperature range .................. C 65 c to 150 c lead temperature (soldering, 10 sec) ................... 300 c *the boost voltage is generated by the LTC3305 and is typically 8.45v higher than v4. (note 1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 top view fe package 38-lead plastic tssop 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 boost v4 v3 auxp auxn v2 v1 ngate1 ngate2 ngate3 ngate4 ngate5 ngate6 ngate7 ngate8 ngate9 batx baty ovflt cm cp nc mode en1 en2 term1 term2 v reg i set v h v l ctbat cton ctoff ptcflt done bal uvflt 39 gnd ja = 28c/w exposed pad (pin 39) is gnd, must be soldered to pcb nc = no connect order information lead free finish tape and reel part marking* package description temperature range LTC3305efe#pbf LTC3305efe#trpbf LTC3305 fe 38-lead plastic tssop C 40oc to 125c LTC3305ife#pbf LTC3305ife#trpbf LTC3305 fe 38-lead plastic tssop C 40oc to 125c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http: //www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http: //www.linear.com/tapeandreel/. some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix. (http: //www.linear.com/product/LTC3305#orderinfo) lt c3305 3305fb
3 for more information www.linear.com/LTC3305 electrical characteristics symbol parameter conditions min typ max units v bat individual battery voltage l 4 16 v v4 voltage at the top of the battery stack l 12 64 v v reg regulator output voltage i vreg = 200a l 2.4 2.5 2.6 v v reg,uv regulator undervoltage threshold regulator voltage falling l 1.7 2.1 v hysteresis 125 mv maximum guaranteed load current v reg > v reg,uv l 3 ma regulator short circuit current limit v reg = 0v 8 15 22 ma shutdown current measured at v4, boost-v4 = 0v measured at v3, v2, v1, auxp, boost l 16 33 0 50 1 a a supply current while balancing battery 1 (notes 4, 5) measured at v4 measured at v3 measured at v2 measured at v1 900 0 0 150 1350 1 1 225 a a a a supply current while balancing battery 2 (notes 4, 5) measured at v4 measured at v3 measured at v2 measured at v1 C70 900 0 150 C45 1350 1 225 a a a a supply current while balancing battery 3 (notes 4, 5) measured at v4 measured at v3 measured at v2 measured at v1 C70 900 150 C45 0 1350 225 1 a a a a supply current while balancing battery 4 (notes 4, 5) measured at v4 measured at v3 measured at v2 measured at v1 C70 1050 C45 0 0 1575 1 1 a a a a supply current while balancing any battery measured at auxp measured at auxn C195 165 C130 245 a a supply current in off state (mode = 0) measured at v4, boost-v4 = 0v measured at v3, v2, v1, auxp, boost 100 0 150 1 a a boost pin current while balancing any battery (notes 4, 5) 220 330 a v iset i set servo voltage 50a< i iset < 150a l 1.18 1.2 1.22 v i vh, i vl current out of v h and v l pins i iset = 100a l 31.3 33.3 35.3 a i ngate current for external nmos turn on (note 5) leakage current in shutdown ngate3 current, i iset = 100a all other ngate currents, i iset = 100a en1 = en2 = 0 l l l 2.0 1.0 C2 2.2 1.1 2.4 1.2 2 ma ma a current programmable range ngate3 current all other ngate currents l l 1 0.5 3 1.5 ma ma v bat,uv undervoltage falling battery threshold (note 6) v l = 0.4v v l = 1.6v l l 3.9 15.6 4 16 4.1 16.4 v v undervoltage hysteresis 120 mv undervoltage falling programmable range l 4 16 v v bat,ov overvoltage rising battery threshold (note 6) v h = 0.4v v h = 1.6v l l 3.9 15.6 4 16 4.1 16.4 v v overvoltage hysteresis 150 mv overvoltage rising programmable range l 4 16 v the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. (note 2) v1 = 13.2v, v2 = 26.4v, v3 = 39.6v, v4 = 52.8v, auxp - auxn = 13.2v, r iset = 12.1k lt c3305 3305fb
4 for more information www.linear.com/LTC3305 the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. (note 2) v1 = 13.2v, v2 = 26.4v, v3 = 39.6v, v4 = 52.8v, auxp - auxn = 13.2v, r iset = 12.1k note 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2. the LTC3305 is tested under pulsed load conditions such that t j t a . the LTC3305e is guaranteed to meet specifications from 0oc to 85oc junction temperature. specifications over the C40oc to 125oc operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the LTC3305i is guaranteed over the C40c to 125c operating junction temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance, and other environmental factors. the junction temperature (t j , in c) is calculated from the ambient temperature (t a , in c) and power dissipation (p d , in watts) according to the formula: t j = t a + (p d ? ja ), where ja (in c/w) is the package thermal impedance. symbol parameter conditions min typ max units ptc fault threshold |bat-auxp| falling 0.8 1 1.2 v hysteresis 100 mv v terminate |bat-auxp| for which balancing is terminated term2 = 0, term1 = 0 term2 = 0, term1 = 1 term2 = 1, term1 = 0 term2 = 1, term1 = 1 l l l l 5.0 17.5 40 85 12.5 25 50 100 20.0 32.5 60 115 mv mv mv mv minimum (boost- v4 ) voltage for operation l 6.7 6.95 7.2 v hysteresis 180 mv maximum (boost- v4 ) voltage regulated l 8.45 8.75 v hysteresis 200 mv r nmos charge pump nmos switch on resistance measured at 10ma 20 r pmos charge pump pmos switch on resistance measured at 10ma 55 t bat maximum time a single battery stays connected to the auxiliary battery ctbat = 10nf 4.5 5 5.5 sec t on maximum stack balancing termination time mode = 0, cton = 10nf 0.43 0.48 0.53 hrs t off off time after stack balance termination mode = 0, done = 0, ctoff = 10nf 0.43 0.48 0.53 hrs v ih digital input high voltage en1, en2, mode, term1, term2 pins l 1.2 v v il digital input low voltage en1, en2, mode, term1, term2 pins l 0.4 v i ih, i il leakage current en1, en2, mode, term1, term2 pins; 2.5v at pin l C1 1 a v ol output low voltage batx, baty, bal, done, uvflt, ovflt, ptcflt pins; 3ma into pin l 27.5 150 mv i oh output high leakage current batx, baty, bal, done, uvflt, ovflt, ptcflt pins; 6v at pin 1 a thermal shutdown threshold (note 7) rising temperature 155 c thermal shutdown hysteresis 10 c note 3. continuous operation above the specified maximum operating junction temperature may result in device degradation or failure. note 4. the ngate pin currents are not included in this number. note 5. the ngate5 , ngat e6 , ngate7 pin currents are drawn from the boost pin. all other ngate pin currents are drawn from the v4 pin. the ngate pin currents add to the currents drawn by v4 and boost. note 6. the voltage programmed at the v h and v l pins are gained up to set the undervoltage and overvoltage thresholds of each battery. note 7: this ic includes overtemperature protection intended to protect the device during momentary overload conditions. the maximum junction temperature may be exceeded when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may result in device degradation or failure. electrical characteristics lt c3305 3305fb
5 for more information www.linear.com/LTC3305 typical performance characteristics i ngate vs i iset i ngate vs temperature i iset (a) i ngate (ma) 3305 g07 0.4 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 1.3 1.4 1.5 1.6 1.7 1.8 50 60 70 80 90 100 110 120 130 140 150 all ngate pin currents and ngate3 current 2 v4 = 52.8v, v ngate = 0v uv threshold vs temperature temperature (c) i ngate (ma) 3305 g08 1.00 1.16 1.14 1.12 1.10 1.08 1.06 1.04 1.02 1.18 1.20 ?55 ?35 ?15 5 25 45 65 85 105 125 all ngate pin currents and ngate3 current v4 = 52.8v, v ngate = 0v, r iset = 12k 2 temperature (c) battery voltage (v) 3305 g09 4.75 4.80 5.20 5.15 5.05 5.10 5.00 4.90 4.95 4.85 5.25 ?55 ?35 ?15 255 45 65 10585 125 rising falling r iset = 12.1k r vl = 15k t a = 25c , unless otherwise noted. off state current vs temperature temperature (c) i v4 (a) 3305 g05 75 95 90 85 80 100 105 110 115 120 125 ?55 ?35 ?15 5 25 45 65 85 105 125 v4 = 64v v4 = 52.8v v4 = 12v v iset vs temperature temperature (c) v iset (v) 3305 g06 1.180 1.190 1.185 1.195 1.200 1.205 1.210 1.215 1.220 ?55 ?35 ?15 5 25 45 65 85 105 125 shutdown current vs temperature v reg,uv vs temperature temperature (c) v reg,uv (v) 3305 g03 1.5 1.7 1.6 1.8 1.9 2.0 2.1 2.3 2.4 2.2 2.5 ?55 ?35 ?15 5 25 45 65 85 105 125 rising falling temperature (c) i v4 (a) 3305 g04 15 20 25 35 30 40 45 50 55 ?55 ?35 ?15 5 25 45 65 85 105 125 v4 = 64v v4 = 52.8v v4 = 12v v reg line and load regulation v reg vs temperature temperature (c) v reg (v) 3305 g02 2.00 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 ?55 ?35 ?15 5 25 45 65 85 105 125 i vreg = 3ma, v4 = 12v i vreg = 1ma, v4 = 52.8v i vreg = 0.2ma, v4 = 52.8v current (ma) v reg (v) 3305 g01 0.0 0.4 0.2 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 0 3 6 9 12 15 v4 = 12v v4 = 52.8v lt c3305 3305fb
6 for more information www.linear.com/LTC3305 typical performance characteristics 25mv termination threshold vs temperature uv and ov programming gain ov threshold vs temperature 12.5mv termination threshold vs temperature maximum battery current during ptc fault condition ptc fault threshold vs temperature uv threshold vs temperature temperature (c) battery voltage (v) 3305 g10 9.5 10.3 10.2 9.9 10.1 10.0 9.8 9.6 9.7 10.4 10.5 ?55 ?35 ?15 255 45 65 10585 125 rising falling r iset = 12.1k r vl = 30.1k temperature (c) i v1 (a) 3305 g15 425 475 465 455 445 435 485 495 505 515 525 ?55 ?35 ?15 255 45 65 10585 125 v1 = 13.2v, auxn = auxp = gnd temperature (c) v terminate (mv) 3305 g16 2.5 18.5 16.5 14.5 12.5 10.5 8.5 6.5 4.5 20.5 22.5 ?55 ?35 ?15 255 45 65 10585 125 temperature (c) |v1-auxp| (mv) 3305 g14 900 1075 1100 1125 1150 1050 1000 1025 950 975 925 1175 1200 ?55 ?35 ?15 255 45 65 10585 125 rising v1 = 13.2v, auxn = gnd falling v l or v h (v) v bat,uv /v l or v bat,ov /v h (v/v) 3305 g13 9.5 10.0 10.1 10.2 10.3 9.9 9.7 9.8 9.6 10.4 10.5 0.4 0.5 0.6 1.11.00.90.7 0.8 1.2 1.3 1.51.4 1.6 uv gain ov gain temperature (c) battery voltage (v) 3305 g12 14.4 14.9 15.0 15.1 15.2 14.8 14.6 14.7 14.5 15.3 15.4 ?55 ?35 654525 ?15 5 85 105 125 r iset = 12.1k r vh = 45.3k rising falling ov threshold vs temperature temperature (c) battery voltage (v) 3305 g11 7.20 7.55 7.60 7.65 7.50 7.40 7.35 7.30 7.45 7.25 7.70 ?55 ?35 654525 ?15 5 85 105 125 r iset = 12.1k r vh = 22.6k rising falling 50mv termination threshold vs temperature temperature (c) v terminate (mv) 3305 g17 15 31 29 27 25 23 21 19 17 33 35 ?55 ?35 ?15 255 45 65 10585 125 temperature (c) v terminate (mv) 3305 g18 40 56 54 52 50 48 46 44 42 58 60 ?55 ?35 ?15 255 45 65 10585 125 t a = 25c , unless otherwise noted. lt c3305 3305fb
7 for more information www.linear.com/LTC3305 typical performance characteristics boost charge pump start-up minimum boost voltage vs temperature 100mv termination threshold vs temperature t on , t off vs temperature t b at vs temperature v ol vs temperature v reg start-up 100s/div 500mv/ div cvreg = 2.2f 0v 3305 g24 5ms/div ch2, 0v 5v/div ch1, 0v 2v/div voltage across c boost voltage across c fly 3305 g25 temperature (c) v ol (mv) i = 3ma 3305 g23 15.0 40.0 37.5 35.0 32.5 30.0 27.5 25.0 22.5 20.0 17.5 42.5 45.0 ?55 ?35 ?15 255 45 65 10585 125 temperature (c) time (seconds) ctbat = 10nf (cog) 3305 g22 4.5 5.3 5.2 5.1 5.0 4.9 4.8 4.7 4.6 5.4 5.5 ?55 ?35 ?15 255 45 65 10585 125 temperature (c) time (hours) v4 = 52.8v cton = ctoff = 10nf (cog) 3305 g21 0.450 0.505 0.500 0.495 0.490 0.485 0.480 0.475 0.470 0.465 0.460 0.455 0.510 ?55 ?35 ?15 255 45 65 10585 125 temperature (c) v boost -v4 (v) 3305 g20 6.5 7.0 6.9 6.8 6.7 6.6 7.1 7.2 ?55 ?35 ?15 255 45 65 10585 125 rising falling temperature (c) v terminate (mv) 3305 g19 90 104 106 98 100 102 96 92 94 108 110 ?55 ?35 ?15 255 45 65 10585 125 t a = 25c , unless otherwise noted. lt c3305 3305fb
8 for more information www.linear.com/LTC3305 pin functions boost (pin 1): charge pump output. decouple with a 10f capacitor to v4. v4 (pin 2): positive terminal of battery 4 connects to this pin. battery 4 is connected between v4 and v3. decouple with at least a 10f capacitor to v3. v3 (pin 3): positive terminal of battery 3 connects to this pin. battery 3 is connected between v3 and v2. decouple with at least a 10f capacitor to v2. auxp (pin 4) : positive terminal of the auxiliary cell con - nects to this pin. decouple with at least a 10f capacitor to auxn. auxn (pin 5): negative terminal of the auxiliary cell con - nects to this pin. v2 (pin 6): positive terminal of battery 2 connects to this pin. battery 2 is connected between v2 and v1. decouple with at least a 10f capacitor to v1. v1 (pin 7): positive terminal of battery 1 connects to this pin. battery 1 is connected between v1 and gnd. decouple with at least a 10f capacitor to gnd. ngat e1 (pin 8) : nmos1 gate. connect to the gate terminal of external nmos switch. ngat e2 (pin 9) : nmo s2 gate. connect to the gate terminal of external nmos switch. ngat e3 (pin 10): nmos3 gate. connect to the gate ter - minal of external nmos switch. ngat e4 (pin 11): nmos4 gate. connect to the gate ter - minal of external nmos switch. ngat e5 (pin 12): nmos5 gate. connect to the gate ter - minal of external nmos switch. ngat e6 (pin 13): nmos6 gate. connect to the gate ter - minal of external nmos switch. ngat e7 (pin 14): nmos7 gate. connect to the gate ter - minal of external nmos switch. ngat e8 (pin 15): nmos8 gate. connect to the gate ter - minal of external nmos switch. ngat e9 (pin 16): nmos9 gate. connect to the gate ter - minal of external nmos switch. batx (pin 17) : this pin along with baty indicates which battery in the stack is currently being balanced and to which the fault outputs apply. open drain output. baty (pin 18) : this pin along with batx indicates which battery in the stack is currently being balanced and to which the fault outputs apply. open drain output. ovflt (pin 19) : overvoltage fault. this pin is pulled low when an overvoltage fault condition is detected on a bat - tery. open drain output. uvflt (pin 20): undervoltage fault. this pin is pulled low when an undervoltage fault condition is detected on a battery. open drain output. bal (pin 21) : balancing indicator. this pin is pulled low while the balancing operation is being performed and is in its high impedance state when the part is disabled or the part is in the sleep state. open drain output. done (pin 22) : done indicator. this pin is pulled low when all the batteries in the stack are balanced. this pin is in its high impedance state in shutdown. open drain output. ptcflt (pin 23): ptc fault. this pin is pulled low when the voltage across the ptc thermistor exceeds 1v. it is in its high impedance state at all other times. open drain output. ctoff (pin 24) : a capacitor from this pin to gnd programs the retry time in timer mode. connect to gnd if mode = 1. cton (pin 25) : a capacitor from this pin to gnd programs the maximum time for the balancing operation in timer mode. connect to gnd if mode = 1. ctbat (pin 26) : a capacitor from this pin to gnd programs the maximum time an individual battery in the stack is con - nected to the auxiliary cell during the balancing operation. v l (pin 27): low voltage fault threshold. a resistor from this pin to gnd programs the low voltage fault threshold for each battery in the series stack. works in conjunction with the i set pin. v h (pin 28) : high voltage fault threshold. a resistor from this pin to gnd programs the high voltage fault threshold for each battery in the series stack. works in conjunction with the i set pin. lt c3305 3305fb
9 for more information www.linear.com/LTC3305 i set (pin 29) : reference current pin that servos to 1.2v. a resistor from this pin to gnd programs the gate charge current for the external nmos switches. the reference current is also used to program the undervoltage and overvoltage thresholds. v reg (pin 30) : low voltage regulated output. an inter - nally generated voltage of 2.5v is always present at this pin. the voltage at this pin may be overdriven by a higher external voltage up to 5.5v. this pin has limited current sink capability and will not pull down a higher externally applied voltage. all logic input pins must be referenced to this pin. decouple with a 1f capacitor to gnd. term2 (pin 31) : termination threshold select. this pin along with term1 is used to set the voltage difference between the battery and auxiliary cell at which a battery is deemed balanced. high input impedance pin, do not float. term1 (pin 32) : termination threshold select. this pin along with term2 is used to set the voltage difference between the battery and auxiliary cell at which a battery is deemed balanced. high input impedance pin, do not float. en2 (pin 33) : enable input. the state of the e n1 and e n2 pins is used to indicate the number of batteries in the stack. with both pins at gnd, the part is in shutdown. high input impedance pin, do not float. en1 (pin 34) : enable input. the state of the e n1 and e n2 pins is used to indicate the number of batteries in the stack. with both pins at gnd, the part is in shutdown. high input impedance pin, do not float. mode (pin 35) : mode select. when held high, continuous mode is selected. when held low, timer mode is selected. high input impedance pin, do not float. no connect (pin 36) : this pin is not connected internally. solder this pin to a pad electrically isolated from all other circuit nodes. cp (pin 37): positive terminal of charge pump flying capacitor. connect a 10f capacitor from this pin to cm for charge pump operation. cm (pin 38) : negative terminal of charge pump flying capacitor. connect a 10f capacitor from this pin to cp for charge pump operation. gnd (pin 39) : the exposed pad is ground and must be soldered to pcb ground for electrical connectivity and rated thermal performance. pin functions lt c3305 3305fb
10 for more information www.linear.com/LTC3305 block diagram 37 2 3 6 7 29 28 27 31 32 4 5 38 8 9 10 11 12 13 14 15 16 24 25 26 30 33 34 35 17 18 19 20 21 22 23 gnd cp cm ngate1 v4 v3 v2 v1 i set v h v l term2 term1 auxp auxn ngate2 ngate3 ngate4 ngate5 ngate6 ngate7 ngate8 ngate9 ctoff cton ctbat v reg en2 36 no connect en1 mode batx baty bal ovflt uvflt done ptcflt 1 gate drive boost charge pump low voltage regulator termination sense comparator control logic bandgap reference 1.2v thermal shutdown ot 3305 bd mirror v4 uv/ov timers 39 + ? mux lt c3305 3305fb
11 for more information www.linear.com/LTC3305 operation the LTC3305 balancer is intended to be used in conjunc - tion with a separate pre-existing battery stack charger as part of a high performance battery system. the balancing operation itself is stand-alone and can operate independent of whether the battery stack is being charged, discharged, or both. that being said, because the LTC3305 balances voltages, it works best if the voltage readings are stable, which is more true when the battery stack is not being charged or discharged. nevertheless, it will properly bal - ance the battery voltages when the stack is being concur - rently charged and/or discharged, since the voltage across the batteries will average out over time as the LTC3305 repeatedly cycles through them. like all balancers, the lt c3305 will slightly net-discharge the stack in the absence of a separate charger. the LTC3305 balances batteries using an auxiliary cell or an alternate storage cell as a charge reservoir. external nmos switches are controlled in a preprogrammed sequence to connect each battery in the stack to an auxiliary cell. charge is transferred to or from the auxiliary cell when it is connected to a battery. the LTC3305 can operate in one of two modes program- mable via the mode pin. timer mode (mode = 0) the balancing operation begins once the c boost capacitor is charged to at least 6.95v. the bal pin is pulled low, indicating that the part is enabled and balancing the bat - tery stack. the termination voltage, v terminate , is the difference in voltage between the auxiliary cell and the battery connected to the auxiliary cell for which a battery is considered to be balanced. v terminate is programmed via the term1 and term2 pins to one of four preset voltages as shown in table 1. table 1. termination voltages term1 term2 v terminate 0 0 12.5mv 1 0 25mv 0 1 50mv 1 1 100mv the balancing operation begins with the negative terminal of the auxiliary cell connected to the negative terminal of bat1, the lowest battery in the stack. referring to figure 1, the bottom switches n1 and n9 that connect the negative terminal of bat1 to the auxiliary cell s negative terminal are first turned on. to turn on an external nmos switch, the current source at the ngate pin connected to the gate of the external nmos is turned on and a gate source voltage is developed across an external resistor. after an internally set delay of 35ms, the voltages across the auxiliary cell and bat1 are compared by the termina - tion sense comparator. if the voltage difference between the auxiliary cell and bat1 is less than the selected termination voltage, the battery is deemed to be balanced with respect to the auxiliary cell and the bottom switches are turned off by turning off the corresponding ngate pin currents. the next battery in the stack is then connected to the auxiliary cell. figure 1. external switch arrangement for a 4- battery balancing application ngate5 n5 n4 n6 ngate4 bat4 n3b ngate3 ngate2 n3a bat3 bat2 bat1 3305 f01 + + + + + aux ptc ngate6 ngate1-9 LTC3305 auxp auxn n2 n7 n8 n9 ngate7 ngate8 ngate1 n1 ngate9 9 lt c3305 3305fb
12 for more information www.linear.com/LTC3305 operation table 2. top and bottom switch arrangement en1, en2 battery being balanced top switches bottom switches 1,1 (4 bat app) battery 1 n2, n7 n1, n9 battery 2 n3, n6 n2, n8 battery 3 n4, n7 n3, n9 battery 4 n5, n6 n4, n8 1,0 (3 bat app) battery 1 n2, n7 n1, n8 battery 2 n4, n6 n2, n9 battery 3 n5, n7 n4, n8 0,1 (2 bat app) battery 1 n7 n9 battery 2 n5 n8 if the voltage difference between the auxiliary cell and bat1 is greater than the selected termination voltage, the top nmos switches n2 and n7 that connect the positive terminal of bat1 to the auxiliary cell s positive terminal through the ptc thermistor are turned on. after a second internally set delay of 35ms, the termination sense com - parator starts monitoring the voltages across the auxiliary cell and the battery. the battery stays connected to the auxiliary cell until the voltage difference decreases to v terminate or a t bat timeout occurs (t bat is the maximum time that a battery remains connected to the auxiliary cell and is programmed by a capacitor on the ctbat pin). this timer is reset each time the auxiliary cell is connected to a different battery. at this point, all switches are turned off and the next bat - tery in the stack is connected to the auxiliary cell. after the switches have been turned off, an internal 40ms delay provides a break-before-make time after which the nega - tive terminal of the next battery in the stack is connected to the negative terminal of the auxiliary cell via its bottom switches. table 2 shows the top and bottom switches used to connect each battery for different battery stack configurations. when only the bottom switches are on, there is a conduction path between the auxiliary cell and the battery through the body diodes of the top switches. current will flow through this conduction path if the aux - iliary cell and the battery are more than two diode drops apart. the current is limited by the ptc resistor. in this fashion each battery in the stack is connected to the auxiliary cell and the batteries in the stack will be balanced. an internal clamp circuit protects the LTC3305 when the voltage difference between the battery being balanced and the auxiliary cell is greater than 1v. with a 13.2v difference, the clamp draws 475a of current. in the worst case scenario, a 16v difference may appear between the auxiliary cell and a battery. the internal clamp draws 600a of current in this scenario. in the state when both the top and bottom side switches are turned on, the ptcflt pin will be pulled low if the voltage difference between the battery being balanced and the auxiliary cell is greater than 1v. if during the balancing operation the voltage difference becomes less than 1v, the ptcflt pin returns to its high impedance state. the batx and baty pins indicate which battery in the stack is currently connected to the auxiliary cell as shown in table 3. in shutdown, the batx and baty pins are in a high z state and the bal pin is also in a high z state. table 3. state of batx and baty pins state of operation batx b aty battery 1 connected high z high z battery 2 connected high z 0 battery 3 connected 0 0 battery 4 connected 0 high z once all batteries in the stack are balanced the done pin is pulled low, the bal pin is in its high impedance state and the part is put in a low power off state. a four-battery stack is deemed balanced when the ter - mination sense comparator detects v terminate on five consecutive cycles that connect each of the batteries to the auxiliary cell using the bottom switches only. lt c3305 3305fb
13 for more information www.linear.com/LTC3305 in timer mode, a capacitor at the cton pin programs the maximum time, t on , that the balancing operation can run for. the balancing operation is terminated either when the batteries in the stack are deemed to be balanced or a t on time out occurs. after the balancing operation has been terminated, the LTC3305 is put in a low power off state for a fixed time, t off . the t off time is programmed by a capacitor at the ctoff pin. in the off state, the bal pin is put in its high impedance state. once t off times out, the LTC3305 is put back in its on state and the balancing operation begins again. the t on timer may be defeated by tying the cton pin to gnd. in this scenario, the LTC3305 will enter the off state only when all the batteries in the stack are deemed to be balanced. continuous mode (mode = 1) in the continuous mode of operation the part functions in much the same way as in timer mode with the following differences. 1. there is no on or off state. the cton and ctoff pins must be tied to gnd in continuous mode. the balanc - ing operation continues even if the stack is in balance. the balancing operation is terminated only if the part is put in shutdown. the bal pin is always pulled low in continuous mode. 2. in timer mode, if the termination comparator senses that a battery is balanced to the auxiliary cell with only the bottom plates connected, the balancing operation on that battery is terminated. this is not the case in continuous mode. in continuous mode the top switches are turned on and the balancing operation on a battery is terminated only by a t bat time out. since the auxiliary cell remains connected to the battery until a t bat time out occurs, its voltage can change before it connects to the next battery in the stack. as a result, when the stack is balanced and the done pin is pulled low, the voltages across the individual batteries in the stack may differ by more than the programmed v terminate . in the worst case when the capacity of the auxiliary cell is much smaller than the battery, the individual battery operation voltages could differ by up to twice the programmed v terminate when balanced. charge pump operation the LTC3305 uses external nmos devices as switches to connect a battery to the auxiliary cell. the LTC3305 has a charge pump that generates the higher voltage required to turn on some of the external nmos switches. two external capacitors c f ly and c boost , two diodes d1 and d2, and resistors r1 and r2 are required for charge pump operation as shown in figure 2. when the LTC3305 is enabled, the charge pump is turned on. c f ly initially charges with a current i chg through external diode d1, resistor r1 , and the internal nmos switch n1 to gnd. when c f ly is charged to 10.5v, an internal comparator switches the internal nmos switch off and turns on switch p1 . c f ly connects to c boost through diode d2, resistor r2 and the internal pmos switch p1. charge is transferred from c f ly to c boost with a current i dischg . when c f ly is discharged to 9.5v, it is disconnected from c boost , recharged back up to 10.5v , and then reconnected to c boost . in this fashion the voltage across c boost is built up. figure 2. charge pump operation i chg r1 r2 d1 d2 v4 p1 n1 boost cboost 3305 f02 c f ly cm cp i dischg LTC3305 lt c3305 3305fb
14 for more information www.linear.com/LTC3305 operation once the c boost capacitor has 6.95v across it, balancing begins. when c boost is charged to 8.45v, the charge pump operation is disabled and c f ly remains connected to c boost . charge pump operation resumes when c boost discharges to 8.25v. undervoltage and overvoltage fault detection the undervoltage and overvoltage thresholds can be programmed using the resistor at the i set pin in con- junction with resistors at the v l and v h pins. the voltage present at the v l or v h pin programs the corresponding fault threshold to 10 that voltage for each battery in the stack. an internal amplifier accurately gains up the voltage at the v l and v h pins and shifts the threshold voltage to the appropriate battery common mode level. the v l and v h pins have a programming range from 0.4v to 1.6v. the internal undervoltage and overvoltage comparators may not trip correctly for a program voltage outside this range. an internal clamp prevents the thresholds from being programmed to greater than 20v. when an undervoltage or overvoltage fault condition is detected, the corresponding uvflt or ovflt pin is pulled to gnd. the balancing operation is not interrupted during this time. if an undervoltage or overvoltage fault condition goes away during the balancing operation, the correspond - ing fault pin returns to its high impedance state. if the undervoltage and overvoltage fault detection is not needed, the v l and v h pins must be tied to gnd. the uvflt and ovflt pins may either be tied to gnd or left floating. low voltage regulator the LTC3305 has an always on regulator that provides 2.5v at the v reg pin. the v reg pin may be driven externally up to 5.5v. the v reg pin cannot sink current and will not pull down an externally applied voltage. the regulator can source up to 3ma of current. if more than 3ma of current is drawn from the regulator, the v reg voltage will drop below its undervoltage threshold, disabling the LTC3305 and terminating the balancing operation. the balancing operation restarts when the regulator recovers from its undervoltage state. in short circuit, the v reg current is limited to 15ma . the v reg pin should be decoupled with at least a 1f capacitor to gnd. thermal shutdown the LTC3305 has an overtemperature detect circuit that shuts down the balancing operation when the internal silicon junction temperature exceeds 155 c. the LTC3305 resumes balancing when the temperature drops to 145c. in thermal shutdown, the low voltage regulator remains powered. balancing battery stacks with two or three batteries the LTC3305 can also be configured to balance battery stacks of two or three batteries. the state of the enable pins tells the LTC3305 to select the correct switch sequencing. for a two battery stack, the LTC3305 must be enabled with en1 = 0 and en2 = 1. for a three battery stack, the LTC3305 must be enabled with e n1 = 1 and e n2 = 0. the external nmos switch arrangements for a two-battery and three-battery application are shown in figures 3 and 4 respectively. if pin ngat e6 is unused, it must be con - nected to the boost pin. all other unused ngate pins must be connected to v4 as shown in figures 3 and 4. a two battery stack is deemed balanced if the termination sense comparator senses the voltage difference between the auxiliary cell and the battery is less than v terminate on three successive cycles when the auxiliary cell and a battery are connected using only the bottom switches. in the case of a three battery stack, four successive cycles are required to deem the stack balanced. lt c3305 3305fb
15 for more information www.linear.com/LTC3305 figure 3. two-battery application showing external switch arrangement 4 4 bat2 22f 25v 10f 25v 249 1.33k 6.04k 10f 25v 10f 25v 10f 25v 6.04k 6.04k 6.04k d2 d1 bat1 3305 f03 aux auxp LTC3305 ngate5, 7, 8, 9 ngate1-4 ngate6 boost v1 v2 v3 v4 auxn gnd ptc + v reg en1 en2 mode term1 term2 done batx baty cton ctoff ctbat v l v h i set uvflt ovflt bal ptcflt 10nf 100k each 100nf 22nf 27.4k 42.2k 12.1k 1f 6v + + ngate5 all nmos devices = sir882dp d1, d2 = cmmsh1-100 cm cp ngate7 ngate8 ngate9 operation lt c3305 3305fb
16 for more information www.linear.com/LTC3305 figure 4. three-battery application showing external switch arrangement 10f 25v 10f 25v 10f 25v 10f 25v 10f 25v 249 d1 d2 6.04k 6.04k 6.04k 6.04k 6.04k 6.04k 6.04k 6.04k 1.33k 3305 f04 auxp LTC3305 ngate1, 2, 4-9 boost v1 v2 v4 v3 ngate3 auxn gnd v reg en1 en2 mode term1 term2 done batx baty cton ctoff ctbat v l v h i set uvflt ovflt bal ptcflt 1f 6v cm cp 8 bat2 bat3 + + + bat1 aux + ptc 10nf 100k each 100nf 22nf 10f 25v 27.4k 42.2k 12.1k ngate6 ngate8 ngate7 ngate9 ngate1 ngate2 ngate4 ngate5 all nmos switches = sir882dp d1, d2 = cmmsh1-100 operation lt c3305 3305fb
17 for more information www.linear.com/LTC3305 selecting the ptc thermistor a ptc thermistor is a type of resistor with a positive tem - perature coefficient that serves as a protection device by limiting its current above a certain threshold. the ptc device limits the peak current that transfers charge between the auxiliary cell and the battery. when the voltage across the ptc is small, the power dissipated in the ptc is small and the ptc resistance remains constant. as the voltage across the ptc increases, power dissipation in the ptc increases which causes the ptc temperature to rise. when the tem - perature reaches the curie temperature, further increases in voltage will cause the ptc resistance to increase rapidly, which limits the current through the device and thus limits the power dissipation in the ptc. this behavior is shown in the ptc current voltage characteristics in figure 5a . in this fashion the ptc serves to protect the external nmos switches from operating outside of their soa region. as seen in the ptc current voltage characteristics in figure 5a , when the ptc has a small voltage or a high voltage across it, the current flowing through it is small. for small voltages, this is ok since the battery and the auxiliary cell are close to balance. for high voltages, this slows down balancing. to increase balance currents at high voltages a power resistor can be placed in parallel with the ptc device, as shown in figure 5b . additionally, multiple ptc resistors may be connected in parallel to increase current flow at all voltages. ptc devices are manufactured in two styles : ceramic and poly fuse. only a ceramic style ptc device should be used in this application. poly fuse devices have a very limited number of lifetime trip cycles and are not suitable in a balancing application. the ptc must be selected such that power dissipation through the external nmos switches never exceeds their rated soa power dissipation value. refer to table 4 for a list of recommended ptc thermistors. applications information table 4. recommended ceramic ptc thermistors part number manufacturer voltage resistance () ptg l7sarr47m1b51b0 murata 16v 0.47 ptglasar r27m1b51b0 murata 16v 0.27 ptglesar r15m1b51b0 murata 16v 0.15 ptg l12ar1r2h2b51b0 murata 30v 1.2 2381 663 51121 vishay 30v 0.7 2381 663 51321 vishay 30v 0.5 2381 664 52021 vishay 30v 0.3 voltage current 3305 f05a curie point voltage current 3305 f05b ptc resistor in parallel with a resistor single ptc resistor resistor only ptc current voltage characteristics increasing current at large voltage figure 5. ptc behavior (a) (b) lt c3305 3305fb
18 for more information www.linear.com/LTC3305 applications information selecting the auxiliary cell the auxiliary cell must be capable of sourcing and sink - ing current and withstand the maximum voltage of any individual battery in the stack. the esr of the auxiliary cell must be small compared to the ptc thermistor. any voltage dropped across the auxiliary cell esr appears as an offset voltage at the input of the termination comparator. the auxiliary cell used may be a lead-acid battery, a stacked supercapacitor, or a low leakage, high voltage capacitor. when using a supercapacitor stack, the voltage across each individual supercapacitor must not exceed its rated operating voltage. figure 6a shows a battery stack made of 4 batteries, each with a nominal capacity of 50ah, but with a 10% capacity mismatch. with no balancing, the stack capacity is determined by the weakest battery in the stack and is limited to 45ah. in figure 6b , a small capacity auxiliary cell, such as a supercapacitor stack, is used to balance the battery stack. when balanced the stack capacity can be made to approach the nominal capacity of 50ah despite the 10% mismatch. in figure 6c , the auxiliary cell has the same capacity as the batteries in the stack. each of the batteries in figure 6c has a nominal capacity of only 40ah but the stack capac - ity approaches 50ah since the auxiliary cell supplements the capacity of the battery stack. using a large capacity auxiliary cell supplements stack capacity. smaller capac - ity batteries may be used in the stack which helps reduce system costs. precharging the auxiliary cell when using stacked supercapacitors or a single high volt - age capacitor as the auxiliary cell, the auxiliary cell may be initially discharged with a voltage of 0v. at startup, a large voltage exists across the ptc resistor, which will cause the ptc resistance to increase. this limits the cur - rent and hence the charge transfer between the auxiliary cell and the battery it is connected to. the auxiliary cell will be charged very slowly with an indeterminate time, as it sequentially connects to each battery in the stack. once the auxiliary cell has been charged to a point where the ptc device operates as a low resistance device, the balancing process is sped up. a more time efficient solution is to precharge the auxiliary cell to the average voltage of the batteries in the stack. figure 7a shows a circuit using a high voltage buck regulator to precharge the auxiliary cell to v4/4 volts. nmos devices n2a and n2b eliminate a parasitic charging path from battery1 to the auxiliary cell when auxn is connected to gnd through n10. figures 7b and 7c are scope photos showing a complete precharging and balancing operation. 55ah (+10%) 50ah 45ah (?10%) stack capacity =45ah (a) stack capacity 50ah (b) 50ah 55ah (+10%) 50ah 45ah (?10%) 4ah (aux) 50ah ptc stack capacity 50ah (c) 44ah (+10%) 40ah 36ah (?10%) 40ah (aux) 40ah ptc figure 6. increasing stack capacity with an auxiliary cell lt c3305 3305fb
19 for more information www.linear.com/LTC3305 applications information figure 7. precharging the auxiliary cell using the ltc3630a and ltc1440 bat1, bat2, bat3, bat4, auxp-auxn = 2v/div auxn = 10v/div; start, en_3305 = 5v/div time = 20s/div auxp-auxn = 2v/div auxn = 10v/div; start, en_3305 = 5v/div time = 5s/div (a) v reg en1 en2 term2 mode term1 done batx baty cton ctoff ctbat v l v h gnd LTC3305 auxn auxp v1 v2 v3 v4 cm 10f 25v 10f 25v 1f 6v 1.33k 249 6.04k 6.04k d1, d2 = cmmsh1-100 d3 = cmmsh2-80 n1a, n1b, n2, n3a, n3b, n4, n5, n6, n7, n8, n9, n10 - sir882dp cp boost d1 d2 ngate1-9 i set uvflt ovflt bal ptcflt 10f 25v 10f 25v 10f 25v 100h 10f 25v 9 v + v ? v in ngate5 n5 ngate6 ngate7 ngate8 ngate9 n10 n11 n9 n8 n7 n6 n11, n12 = fdv301n 3305 f07 ptc aux 12.1k 42.2k 27.4k 10nf 10nf 100nf 10f 25v ngate4 3.01k 6.04k 174k 6.04k n2a n2b n3a n4 n3b 6.04k 6.04k 6.04k 6.04k ngate3 ngate2 ngate1 bat4 + + + + bat3 in ? out ref hyst gnd ltc1440 in + 5.11m d4, d5, d6 = 1n914 d3 d4 d5 d6 365k bat2 bat1 sw ss fbo i set v prog1 v prog2 ltc3630a gnd fb run s r q qd clk start + 2.2f 100v n12 2.21m 365k 2.21m 681k 40.2k 2.43m n1 (b) (c) lt c3305 3305fb
20 for more information www.linear.com/LTC3305 applications information selection of external nmos switches the external nmos switches must be capable of with- standing a reverse voltage equal to the battery stack volt - age. they should also be capable of carrying dc current up to the ptc thermistor trip point. the maximum power dissipated in the nmos should not cause it to operate outside of its safe operating area. refer to table 5 for a list of recommended nmos switches. programming nmos turn on the nmos switches are turned on by developing a voltage across an external resistor from the gate to the source. the current through the resistor is delivered from the ngate pins and is programmed by the current at the i set pin. the internal current sources that provide the ngate pin currents operate from the v4 and boost supplies as shown in the block diagram. the boost pin voltage is regulated at 8.45v greater than v4. it is recommended that the gate turn on voltage be set to no more than 7.5v . the current flowing through the gate turn on resistor connected to the ngat e3 pin is given by : i ngate3 = 26.4v r iset the current flowing through the other ngate pins is given by: i ngate = 13.2v r iset the ngat e3 current has a programmed range from 1ma to 3ma . all other ngate currents have a programmed range from 500a to 1.5ma. the ngate current initially charges the gate capacitor of the nmos device to turn it on. the external gate source resistor maintains a constant gate to source voltage on the nmos device. programming a higher current reduces the nmos device turn on time. programming a large gate source voltage reduces the on resistance of the nmos device. during turn off, the gate capacitor discharges through the gate source resistor. programming undervoltage and overvoltage thresholds referring to the block diagram, the voltage at the i set pin is servoed to 1.2v . an external resistor, r iset , from this pin to gnd programs a current which is divided down and mirrored to the v l and v h pins. the i set pin current has a programmed range from 50a to 150a. the i set pin current is given by: i iset = 1.2v r iset the current out of the v l and v h pins is given by: i vl = i vh = i iset 3 external resistors r vl from the v l pin to gnd and r vh from the v h pin to gnd program the undervoltage and overvoltage thresholds for each battery. the undervolt - age threshold for a battery is given by : v bat,uv = 4v r vl r iset the overvoltage threshold for a battery is given by : v bat,ov = 4v r vh r iset programming the t b at parameter the t bat parameter is programmed using a capacitor from the ctbat pin to gnd. t bat is given by: t bat = 5sec c tbat 10nf a c0g type capacitor is recommended due to its superior temperature characteristics. programming the t on and t off parameters the t on parameter is programmed by a capacitor from the cton pin to gnd. t on is given by: t on = 0.48hrs c ton 10nf table 5. recommended nmos switches part number manufacturer i ds(max) v dc(max) sir882dp vishay 60a 100v sis892dn vishay 25a 100v ipd70n10s3-12 infineon 70a 100v ipb35n10s3l-26 infineon 35a 100v rjk1051dpb renesas 60a 100v rjk1054dpb renesas 92a 100v lt c3305 3305fb
21 for more information www.linear.com/LTC3305 applications information the t off parameter is programmed by a capacitor from the ctoff pin to gnd. t off is given by: t off = 0.48hrs c toff 10nf c0 g type capacitors are recommended due to their superior temperature characteristics. in the continuous operation mode (mode = 1), the cton and ctoff pins are unused and should be connected to gnd. selecting charge pump components referring to figure 2, recommended values for r1, r2 and c f ly are 249, 1.33k & 10f respectively for all ap- plications. for applications in which v4 is no lower than 32v a 10f capacitor is recommended for c boost . for applications which may have lower voltages at v4, the recommended value for c boost is 22f. schottky diodes with a breakdown voltage larger than the maximum v4 voltage are recommended for diodes d1 and d2. selecting decoupling capacitors decoupling capacitors of at least 10f must be placed across each battery, from the boost pin to v4 and from the auxp pin to the auxn pin. these capacitors must be placed as close as possible to the LTC3305. the capacitors must be capable of withstanding the maximum voltage across each battery. capacitors with an x5r or x7r type dielectric should be used. thermal considerations and limiting on-chip power dissipation excessive on-chip power dissipation will cause the LTC3305 to enter thermal shutdown. it is important to understand the source of the power dissipation and how power dissipation can be reduced. the two contributions of on-chip power dissipation on the LTC3305 that may be controlled by the user are the loading on the low voltage regulator and the power dissipated through the current sources that provide the ngate pin currents. the low voltage linear regulator provides a 2.5v output. any current provided by the regulator will cause power dissipation in the internal switch connected from v4 to v reg , which causes die temperature to increase. in figure 8, an external switching regulator generates a 3.3v rail that back drives the v reg pin and provides power to the external microprocessor and other low voltage circuits. there is no on-chip loading on the v reg pin and thus no on chip power dissipation in the low voltage regulator. in figure 8, external resistors r1, r2, r3, r4, and r5 are in series with the on-chip current sources that provide ngate pin current. these resistors reduce the voltage across the on-chip current sources and thus reduce on-chip power dissipation. as an example, the current source at ngat e1 delivers current from the v4 pin. when this current source is turned on, the voltage across it is v4-v ngat e1 . for a typical application with v4 = 52.8v, programmed i ngate = 506a and v ngat e1 = 6.12v , the on-chip power dissipated in the current source is 23mw. in figure 8, resistor r1 operates with approximately 30.5v across it. the on-chip power dissipated in the current source is reduced to ap - proximately 8mw. in similar fashion resistors r2, r3, r4, and r5 reduce the on-chip power dissipation on the respective current sources. when choosing these resistors it is recommended to have the internal current sources biased with at least 6v across them under all operating conditions. power dissipation through the on-chip current sources may be further reduced by programming a lower gate current through the ngate pins. balancing battery stacks with more than four batteries to balance battery stacks that have more than four batter - ies, multiple LTC3305 devices may be stacked together. in this scenario, it is recommended that each LTC3305 be run in continuous mode and at least one battery in each sub-stack of four is common to two LTC3305s. each LTC3305 needs an auxiliary cell for the balancing opera - tion. figure 9 shows an eight battery stack being balanced using three LTC3305 devices connected together. figure 10 shows a stack of six batteries being balanced using two LTC3305 devices. to balance a battery stack with n batteries, the minimum number of LTC3305 devices required is [(n-1)/3] rounded up to the nearest integer. in this calculation, each LTC3305 is assumed to be used in a four-battery configuration and at least one battery interleaves two LTC3305 devices. lt c3305 3305fb
22 for more information www.linear.com/LTC3305 applications information figure 8. 4-battery application with external resistors to limit power dissipation v reg en1 en2 term2 mode term1 done batx baty cton ctoff ctbat v l v h gnd LTC3305 auxn auxp v1 v2 v3 v4 cm 10f 25v 10f 25v 1.33k 249 12.1k 12.1k cp boost d1 d2 ngate1-9 i set uvflt ovflt bal ptcflt 10f 25v 10f 25v 10f 25v 10f 25v 10f 25v 9 all nmos switches = sir882dp d1, d2 = cmmsh1-100 3.3v 100k each ltc3630a buck regulator microprocessor ngate5 ngate6 ngate7 ngate8 ngate9 3305 f08 ptc = ptgl13aror8h2b71b0 aux 23.7k 93.1k 59k 10nf 100nf 10nf ngate4 6.04k 12.1k 12.1k 12.1k 12.1k 12.1k 12.1k 12.1k r4 20k r5 ngate3 ngate2 ngate1 bat4 bat3 10k r3 37.4k r2 r1 60.4k bat2 bat1 + + + + + when multiple lt c3305 devices are stacked, the logic out - put pins may need to be level shifted and ground referred. in figure 9, optical isolators are used for level shifting. figure 11 shows an application in which an eight battery stack is balanced using two LTC3305 devices and two auxiliary cells. bat1, bat2, bat3, and bat4 are balanced to each other using the lower LTC3305 whereas bat5, bat6, bat7, and bat8 are balanced to each other by the upper LTC3305. pcb considerations in operation the LTC3305 can dissipate large amounts of power which can increase die temperature and cause the part to enter thermal shutdown. the exposed pad of LTC3305 must be well soldered to the pcb to provide adequate heat sinking. the exposed pad also provides an electrical gnd to the LTC3305. the no-connect pin on the LTC3305 must be soldered to a pad on the pcb and must be electrically isolated from any other circuit node. the trace that connects the auxp pin to the positive terminal of the auxiliary source must be as close to the auxiliary source positive terminal as possible. otherwise the trace impedance adds to the esr of the auxiliary cell which manifests itself as an offset at the internal termina- tion comparator. the v1, v2, v3 and v4 traces must be kelvin connected directly to the battery terminal and must not share a com - mon trace through which high balance current will flow. any voltage drop in these traces also manifests itself as an offset voltage at the termination comparator input. lt c3305 3305fb
23 for more information www.linear.com/LTC3305 applications information figure 9. three LTC3305 devices connected to balance eight lead-acid batteries 3305 f07 v reg en1 en2 mode term1 term2 done batx baty cton ctoff ctbat vl v h gnd LTC3305 auxn auxp v1 v2 v3 v4 cm 10f 25v 10f 25v 5.49k 5.49k cp boost ngate1-9 ngate1c-9c i set uvflt ovflt bal ptcflt 10f 25v 10f 25v 10f 25v 10f 25v 9 ngate5c ngate6c ngate7c ngate8c ngate9c ptc aux3 20k 32.4k 8.06k 10nf ngate4c d5 249 1.33k d6 + + + + + + + + 2.74k 5.49k 5.49k 5.49k 5.49k 5.49k ngate3c ngate2c ngate1c bat8 bat7 5.49k bat6 bat5 bat4 bat3 bat2 bat1 1f 6v 2.43k cpc1301g cpc1301g to p 2.43k 2.43k 2.43k 2.43k 2.43k 2.43k 100k 100k 100k 100k 100k 100k 100k v reg en1 en2 mode term1 term2 done batx baty cton ctoff ctbat vl v h gnd LTC3305 auxn auxp v1 v2 v3 v4 cm 10f 25v 10f 25v 5.49k 5.49k cp boost ngate1-9 ngate1a-9a i set uvflt ovflt bal ptcflt 10f 25v 10f 25v 10f 25v 10f 25v 9 ngate5a ngate6a ngate7a ngate8a ngate9a ptc aux1 8.06k 10nf ngate4a 2.74k 5.49k 5.49k 5.49k 5.49k 5.49k ngate3a ngate2a ngate1a 5.49k 1f 6v 3.3v v reg en1 en2 mode term1 term2 done batx baty cton ctoff ctbat vl v h gnd LTC3305 auxn auxp v1 v2 v3 v4 cm 10f 25v 10f 25v 5.49k 5.49k cp boost ngate1-9 ngate1b-9b i set uvflt ovflt bal ptcflt 10f 25v 10f 25v 10f 25v 10f 25v 9 ngate5b ngate6b ngate7b ngate8b ngate9b ptc aux2 20k 32.4k 8.06k 10nf ngate4b 2.74k 5.49k 5.49k 5.49k 5.49k 5.49k ngate3b ngate2b ngate1b 5.49k 1f 6v 32.4k 20k d3 d4 d1 d2 + to p 100k 100k 100k 100k 100k 100k 100k 2.43k 2.43k 2.43k 2.43k 2.43k 2.43k 2.43k to p 100k 100k 100k 100k 100k 100k 100k 249 1.33k 249 1.33k all nmos devices = sir882dp d1, d2, d3, d4, d5, d6 = cmmsh1-100 10f 25v 10f 25v 10f 25v + + lt c3305 3305fb
24 for more information www.linear.com/LTC3305 applications information figure 10. two LTC3305 devices connected to balance six lead-acid batteries with andd done indicator v reg en1 en2 term2 mode term1 done batx baty cton ctoff ctbat v l v h gnd LTC3305 auxn auxp v1 v2 v3 v4 cm 10f 25v 10f 25v 1.33k 6.04k 6.04k all nmos devices = sir882dp d1, d2, d3, d4 = cmmsh1-100 cp boost d3 249 d4 ngate1-9 i set uvflt ovflt bal ptcflt 10f 25v 10f 25v 10f 25v 10f 25v ngate5b ngate6b ngate7b ngate1b-9b ngate8b ngate1b ngate9b 3305 f08 ptc aux2 27.4k 10nf 10f 25v 42.2k 12.1k ngate4b 3.01k 6.04k 6.04k 9 6.04k 6.04k 6.04k ngate3b ngate2b bat5 475k 1f 6v 10f 25v 475k 475 6.04k bat6 + + + + + + + + bat4 bat3 v reg en1 en2 term2 mode term1 done batx baty cton ctoff ctbat v l v h gnd LTC3305 auxn auxp v1 v2 v3 v4 cm 10f 25v 10f 25v 1.33k 249 6.04k 6.04k cp boost d1 d2 ngate1-9 i set uvflt ovflt bal ptcflt 10f 25v 10f 25v 10f 25v 10f 25v ngate5a ngate6a ngate7a ngate1a-9a ngate8a ngate1a ngate9a ptc 9 aux1 27.4k 10nf 42.2k 12.1k ngate4a 3.01k 6.04k 6.04k 6.04k 6.04k 6.04k ngate3a ngate2a bat2 1f 6v 6.04k bat1 lt c3305 3305fb
25 for more information www.linear.com/LTC3305 applications information 100k 10nf 12.1k v reg en1 en2 term2 mode term1 done batx baty cton ctoff ctbat v l v h gnd LTC3305 auxn auxp v1 v2 v3 v4 cm cp boost i set uvflt ovflt bal ptcflt 249 10f 25v 10f 25v 10f 25v 10f 25v 10f 25v 10f 25v 10f 25v d3 d4 1.33k 1f 6v ngate1-9 9 ngate1b-9b ptc aux2 + 10f 25v ngate6b ngate7b ngate8b ngate9b all nmos devices = sir892dp d1, d2, d3, d4 = cmmsh1-100 6.04k 6.04k 6.04k 6.04k ngate5b 6.04k bat8 + + + + + + + + + bat7 bat6 bat5 ngate4b 6.04k ngate2b 6.04k ngate1b 6.04k ngate3b 3.01k 100k 10nf 12.1k v reg en1 en2 term2 mode term1 done batx baty cton ctoff ctbat v l v h gnd LTC3305 auxn auxp v1 v2 v3 v4 cm cp boost i set uvflt ovflt bal ptcflt 249 10f 25v 10f 25v 10f 25v 10f 25v 10f 25v d1 d2 1.33k 1f 6v ngate1-9 9 ngate1a-9a ptc aux1 3305 f11 ngate6a ngate7a ngate8a ngate9a 6.04k 6.04k 6.04k 6.04k ngate5a 6.04k bat4 bat3 bat2 bat1 ngate4a 6.04k ngate2a 6.04k ngate1a 6.04k ngate3a 3.01k 10f 25v figure 11. eight battery balancer using two LTC3305 devices lt c3305 3305fb
26 for more information www.linear.com/LTC3305 package description please refer to http: //www.linear.com/product/LTC3305#packaging for the most recent package drawings. 4.75 (.187) ref fe38 (aa) tssop rev c 0910 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 19 20 ref 9.60 ? 9.80* (.378 ? .386) 38 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.50 (.0196) bsc 0.17 ? 0.27 (.0067 ? .0106) typ recommended solder pad layout 0.315 0.05 0.50 bsc 4.50 ref 6.60 0.10 1.05 0.10 4.75 ref 2.74 ref 2.74 (.108) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 38-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1772 rev c) exposed pad variation aa lt c3305 3305fb
27 for more information www.linear.com/LTC3305 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 09/15 added timer mode section. modified figure 6 schematic. modified figure 8 schematic. modified figure 9 schematic. 13 16 22 23 b 03/16 updated feature bulleted items and description updated application schematic enhanced operation section 1 1 11 lt c3305 3305fb
28 for more information www.linear.com/LTC3305 related parts typical application part number description comments ltc3300-1 ltc3300-2 high efficiency bidirectional multicell battery balancer balances up to 6 li-ion batteries per ic. stackable to balance large battery stacks lt8584 2.5a monolithic active cell balancer with telemetry interface integrated 6a, 50v switch. stackable to balance large battery stacks ltc4015 multichemistry buck battery charger controller with digital?telemetry system monitors system parameters, pre-programmed maximum power point tracking algorithm ltc4020 55v buck-boost multi-chemistry battery charger capable of charging 4 lead-acid batteries up to 55v ltc4000 high voltage high current controller for battery charging and power management complete high performance battery charger when paired with a dc/dc converter ltc3630a high efficiency, 65v 500ma synchronous step down converter efficiently generates a low voltage rail. synchronous operation for high efficiency ltc2946 wide range i 2 c power, charge and energy monitor measures current, voltage, power, charge and energy in a battery stack up to 100v v reg en1 en2 term2 mode term1 done batx baty cton ctoff ctbat v l v h gnd LTC3305 auxn auxp v1 v2 v3 v4 cm 10f 25v 10f 25v 1.33k 249 6.04k 6.04k d1, d2 = cmmsh1-100 cp boost d1 d2 ngate1-9 i set uvflt ovflt bal ptcflt 10f 25v 10f 25v 10f 25v 10f 25v 10f 25v 9 1f 6v ngate5 ngate6 ngate7 ngate8 ngate9 3305 ta02 ptc aux 12.1k 10nf ngate4 3.01k 6.04k 6.04k 6.04k 6.04k 6.04k 6.04k ngate3 ngate2 ngate1 all nmos devices = sir882dp bat4 + + + + bat3 bat2 bat1 100 + a minimum component application in which an led is used to display status lt 0316 rev b ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/LTC3305 ? linear technology corporation 2015 lt c3305 3305fb

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